DIAMOND Tutorial: Handling the challenges of debugging and reliability
Thursday, March 17, 2011, Grenoble, France.
Time: 17.30 - 20.00
Room: Les Bans, DATE conference centre
At the tutorial, latest results in design error debug and reliable systems
research are presented by speakers from academia and companies including IBM
and Ericsson. The topics include automated debugging, template-based system
level repair, soft error resilient design techniques and graceful degradation
for telecommunication SoCs.
The tutorial is sponsored by an European FP7 project DIAMOND (www.fp7-diamond.eu)
and is moderated by Stephen Scholefield from TransEDA Systems, UK.
17.30-17.40 "A short welcome" by Jaan Raik, Tallinn University of Technology, Estonia
17.40-18.10 "Getting the Best Traces for Automated Debugging",
André Sülflow, Görschwin Fey, Rolf Drechsler, University of Bremen, Germany
Powerful automated debugging approaches have been developed recently.
The talk explains these debuggers and shows how their performance
depends on the failure traces considered.
18.10-18.40 "Automated Diagnosis and Repair of Simple Software"
Robert Könighofer, Georg Hofferek, Roderick Bloem, Graz University of Technology, Austria
We present an approach for automated fault localisation and correction
in erroneous software. The approach is based on symbolic execution and
SMT-solving. An implementation operating on incorrect C programs is
under development and will be used for a demo. This is work in progress.
18.40-19.00 Coffee break
19.00-19.30 "Soft error susceptibility analysis in industrial-scale designs"
Sergey Novikov, Eli Arbel, Cindy Eisner, IBM Haifa Research Labs, Israel
Soft error susceptibility analysis is aimed at pointing at those latches
which are most vulnerable to soft error hits. Existence of such
vulnerabilities is usually an indication for reliability problems and
requires mitigation in systems designed for long up times. In this talk we
will overview existing soft error analysis techniques and stress some of
their shortcomings when applied on large-scale designs. Then our approach
developed in DIAMOND, which is designed to address some of the mentioned
limitations, will be presented.
19.30-20.00 "SoC-Level Fault Management based on P1687 IJTAG"
Gunnar Carlsson, Ericsson, Sweden; Artur Jutman, Testonica Lab, Estonia;
Erik Larsson, Linköping University, Sweden
Fault tolerance and fault management mechanisms are necessary means to
reduce the impact of soft errors and wear out in electronic devices.
The semiconductor products manufactured with latest and emerging
processes are increasingly affected by these effects. The presentation
describes a new general scalable fault management architecture based
on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard
allows to create an efficient and regular network for handling fault
detection information, manage test and system resources as a
system-wide background process during system operation.
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