DIAMOND tutorials at the IEEE DDECS Symposium

April 16, 2012, Tallinn. DIAMOND project is to be disseminated on two tutorials at the 15 th IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)symposium to be held in Tallinn, April 18-20, 2012. The following presentations are scheduled as parallel sessions of the DDECS symposium.

Automated Synthesis and Design-Error Repair of Systems.

Georg Hofferek (Graz University of Technology, Austria)

Due to the ever increasing complexity of digital systems, the need for formal verification methods has also been increasing steadily. Verification usually requires some form of specification. Having available a formal specification for a system, one can ask why designers have to bother fixing errors that have been detected. Or, going one step further, why not synthesize the entire system from the specification? We will have a look at two state-of-the-art automated and
correct-by-construction synthesis methods that address these questions. First, we will consider property synthesis, which can be viewed as a game. Second, we show how to benefit from abstraction by uninterpreted functions.

Fault management in an IEEE P1687 (IJTAG) environment.

Erik Larsson (Lund University, Sweden) and Konstantin Šibin (Testonica Lab, Estonia)

To meet the constant demand for performance, it is increasingly common with multi-processor system-on-chips (MPSoCs). As these integrated circuits (ICs) may contain billions of transistors squeezed on a few square centimeter, it is difficult to ensure that they are correct. Defects may escape manufacturing test or develop during operation and, further, ICs manufactured in later semiconductor technologies are increasingly sensitive to environmental disturbances. These defects may be permanent (hard) or transient (soft).

To enable graceful degradation, fault management can be applied to handle eventual defects. Fault management include collection of error statuses from each of the processors, classify the defects, fault mark defective processors, schedule jobs on non-defective processors.

This tutorial consists of three parts. First, we will discuss the need of IEEE P1687 (IJTAG), a standardized mechanism to access embedded features. Second, we will discuss how to make use of IEEE P1697 for fault management. And, third, we will make a demonstration of a fault management solution that makes use of IEEE P1687.

25. 04. 2012