In order to contend chip design issues concerning location/correction of design errors and soft error resilience DIAMOND project will develop:

  • A holistic diagnostic model for design and soft errors;
  • Automated location and correction techniques based on the unified model, both pre-silicon and post-silicon;
  • Implementation of a reasoning framework for location and correction, encompassing word-level techniques, formal, semi-formal, and dynamic techniques;
  • Integration of automated correction with the diagnosis methods.

DIAMOND reaches beyond the state-of-the-art by proposing an integrated approach to location and correction of specification, implementation, and soft errors.  In addition, it considers faults on all abstraction levels, from specification through implementation down to the silicon layout. Handling this full chain of levels allows DIAMOND take advantage of hierarchical diagnosis and correction capabilities incorporating a wide range of error sources.